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1.2 a, ultralow noise, high psrr, rf linear regulator data sheet adp7156 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2016 analog devices, inc. all rights reserved. technical support www.analog.com features input voltage range: 2.3 v to 5.5 v 16 standard voltages between 1.2 v and 3.3 v available maximum load current: 1.2 a low noise 0.9 v rms total integrated noise from 100 hz to 100 khz 1.6 v rms total integrated noise from 10 hz to 100 khz noise spectral density: 1.7 nv/hz from 10 khz to 1 mhz power supply rejection ratio (psrr) 80 db from 1 khz to 100 khz; 60 db at 1 mhz, v out = 3.3 v, v in = 4.0 v dropout voltage: 120 mv typical at i out = 1.2 a, v out = 3.3 v initial accuracy: 0.6% at i load = 10 ma initial accuracy over line, load, and temperature: 1.5% quiescent current: i gnd = 4.0 ma at no load, 7 ma at 1.2 a low shutdown current: 0.2 a stable with a 10 f ceramic output capacitor 10-lead, 3 mm 3 mm lfcsp and 8-lead soic packages precision enable supported by adisimpower tool applications regulation to noise sensitive applications: phase-locked loops (plls), voltage controlled oscillators (vcos), and plls with integrated vcos communications and infrastructure backhaul and microwave links general description the adp7156 is a linear regulator that operates from 2.3 v to 5.5 v and provides up to 1.2 a of output current. using an advanced proprietary architecture, it provides high power supply rejection and ultralow noise, achieving excellent line and load transient response with only a 10 f ceramic output capacitor. there are 16 standard output voltages for the adp7156 . the following voltages are available from stock: 1.2 v, 1.8 v, 2.0 v, 2.5 v, 2.8 v, 3.0 v and 3.3 v. additional voltages available by special order are 1.3 v, 1.5 v, 1.6 v, 2.2 v, 2.6 v, 2.7 v, 2.9 v, 3.1 v, and 3.2 v. the adp7156 regulator typical output noise is 0.9 v rms from 100 hz to 100 khz and 1.7 nv/hz for noise spectral density from 10 khz to 1 mhz. the adp7156 is available in a 10-lead, 3 mm 3 mm lfcsp and 8-lead soic packages, making it not only a very compact solution, but also providing excellent thermal performance for applications requiring up to 1.2 a of output current in a small, low profile footprint. typical application circuit gnd (epad) en ref vin vout adp7156 on off v in = 3.8v v out = 3.3v vout_sense c in 10f c out 10f byp vreg c byp 1f c reg 1f ref_sense c ref 1f 12937-001 figure 1. table 1. related devices model input voltage output current fixed/ adj 1 package adp7158 , adp7159 2.3 v to 5.5 v 2 a fixed/ adj 10-lead lfcsp/ 8-lead soic adp7157 2.3 v to 5.5 v 1.2 a fixed/ adj 10-lead lfcsp/ 8-lead soic adm7150 , adm7151 4.5 v to 16 v 800 ma fixed/ adj 8-lead lfcsp/ 8-lead soic adm7154 , adm7155 2.3 v to 5.5 v 600 ma fixed/ adj 8-lead lfcsp/ 8-lead soic adm7160 2.2 v to 5.5 v 200 ma fixed 6-lead lfcsp/ 5-lead tsot 1 adj means adjustable. 0.1 1 10 100 1k 10 100 1k 10k 100k 1m 10m noise spectr a l densi t y (nv/ 12937-002 c byp =1f c byp =10f c byp =100f c byp =1000f figure 2. noise spectral dens ity at different values of c byp , v out = 3.3 v
adp7156* product page quick links last content update: 11/01/2016 comparable parts view a parametric search of comparable parts evaluation kits ? adp7156 evaluation board documentation data sheet ? adp7156: 1.2 a, ultralow noise, high psrr, rf linear regulator data sheet user guides ? ug-809: evaluating the adp7156 ultralow noise, 1.2 a, fixed output, rf linear regulator tools and simulations ? adi linear regulator design tool and parametric search ? adisimpower? voltage regulator design tool reference materials press ? analog devices? low dropout regulators enable cleaner and faster communications design resources ? adp7156 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all adp7156 engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified.
adp7156 data sheet rev. a | page 2 of 22 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 typical application circuit ............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 input and output capacitors, recommended specifications 4 absolute maximum ratings ............................................................ 5 thermal data ................................................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ............................................. 7 theory of operation ...................................................................... 13 applications information .............................................................. 14 adis impower design tool ....................................................... 14 capacitor selection .................................................................... 14 undervoltage lockout (uvlo) ............................................... 15 programmable precision enable .............................................. 16 start - up time ............................................................................. 17 ref, byp, and vreg pins ......................................................... 17 current - limit and thermal shutdown ................................... 17 thermal considerations ............................................................ 17 printed circuit board (pcb) layout considerations ................ 20 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 22 revision history 5 / 20 16 rev. 0 to rev. a changes to table 2 ............................................................................ 3 changes to programmable precision enable section ................ 16 changes to current - limit and thermal shutdown section .... 17 3 / 20 16 revision 0: initial version
data sheet adp7156 rev. a | page 3 of 22 specifications v in = v out + 0.5 v or 2.3 v, whichever is greater; v en = v in ; i load = 10 ma; c in = c out = 10 f; c reg = c ref = c byp = 1 f; t a = 25c for typical specifications; t a = ?40c to +125c for minimum/maximum specifications, unless otherwise noted. table 2 . parameter symbol test conditions/comments min typ max unit input voltage range v in 2.3 5.5 v load current i load 1.2 a operating supply current i gnd i load = 0 a 4.0 8.0 ma i load = 1.2 a 7.0 12.0 ma shutdown current i in_sd en = gnd 0.2 4 a noise 1 v out = 1.2 v to 3.3 v output noise out noise 10 hz to 100 khz 1.6 v rms 100 hz to 100 khz 0.9 v rms noise spectral density out nsd 10 khz to 1 mhz 1.7 nv/hz power supply rejection ratio 1 psrr 1 khz to 100 khz, v in = 4.0 v, v out = 3.3 v, i load = 1.2 a 80 db 1 mhz, v in = 4.0 v, v out = 3.3 v, i load = 1.2 a 60 db 1 khz to 100 khz, v in = 2.6 v, v out = 1.8 v, i load = 1.2 a 80 db 1 mhz, v in = 2.6 v, v out = 1.8 v, i load = 1.2 a 60 db output voltage accuracy output voltage 2 v out 1.2 3.3 v initial accuracy i load = 10 ma, t a = 25c ?0.6 +0.6 % 10 ma < i load < 1.2 a, t a = 25c ?1.0 +1.0 % 10 ma < i load < 1.2 a, t a = ?40c to +125c ?1.5 +1.5 % regulation line ?v out /?v in v in = v out + 0.5 v or 2.3 v, whichever is greater to 5.5 v ?0.1 +0.1 %/v load 3 ?v out /?i out i out = 10 ma to 1.2 a 0.3 %/a current - limit threshold 4 i limit ref 22 ma vout 1.4 1.8 2.4 a dropout voltage 5 v dropout i out = 600 ma, v out = 3.3 v 60 80 mv i out = 1.2 a, v out = 3.3 v 120 170 mv pull - down resistance en = 0 v, v in = 5.5 v vout v out_pull v out = 1 v 650 v reg v reg_pull v reg = 1 v 31 k ref v ref_pull v ref = 1 v 850 byp v byp_pull v byp = 1 v 650 start - up time 1 , 6 v out = 3.3 v vout t start - up 1.2 ms vreg t reg_start - up 0.6 ms ref t ref_start - up 0.5 ms thermal shutdown 1 threshold ts sd t j rising 150 c hysteresis ts sd_hys 15 c undervoltage thresholds input voltage rising uvlo rise 2.22 2.29 v falling uvlo fal l 1.95 2.02 v hysteresis uvlo hys 200 mv
adp7156 data she et rev. a | page 4 of 22 parameter symbol test conditions/comments min typ max unit vreg uvlo thresholds 7 rising vreguvlo rise 1.94 v falling vreguvlo fal l 1.60 v hysteresis vreguvlo hys 185 mv en input precision 2.3 v v in 5.5 v en input logic high v en _high 1.13 1.22 1.31 v logic low v en _ low 1.05 1.13 1.22 v logic hysteresis v en _ hys 90 mv leakage current ref_sense i ref_sense_ lkg 10 na en i en _ lkg en = v in or gnd 0.01 1 a 1 guaranteed by characterization; not production tested. 2 the adp7156 is available in 16 standard voltages between 1.2 v and 3.3 v, including 1.2 v, 1.3 v, 1.5 v, 1.6 v, 1.8 v, 2.0 v, 2.2 v, 2.5 v, 2.6 v, 2.7 v, 2.8 v, 2.9 v, 3.0 v, 3.1 v, 3.2 v, and 3.3 v. 3 based on an e ndpoint calculation using 10 ma and 1.2 a loads. 4 current - limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. for example, the current limit for a 3 . 0 v output voltage is define d as the current that causes the output voltage to drop to 90% of 3.0 v, or 2.7 v. 5 dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. dropout voltage applies only for output voltages greater than 2.3 v. 6 start - up time is defined as the time between the rising edge of v en to v out , v reg , or v ref being at 90 % of its nominal value. 7 the output voltage is disabled until the vreg uvlo rise threshold is crossed. the vreg ou tput is disabled until the input voltage uvlo rising threshold is crossed. input and output cap acitors, recommended specifications table 3 . parameter symbol test conditions/comments min typ max unit minimum capacitance t a = ?40c to +125c input 1 c in 10.0 f regulator c reg 1.0 f output 1 c out 10.0 f bypass c byp 1.0 f reference c ref 1.0 f capacitor effective series resistance (esr) t a = ?40c to +125c c out , c in r esr 0.001 0.1 c reg , c ref r esr 0.001 0.2 c byp r esr 0.001 2.0 1 the minimum input and output capacitance must be greater than 7.0 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. x7r and x5r type capacitors are r ecommended; y5v and z5u capacitors are not recommended for use with any low dropout regulator .
data sheet adp7156 rev. a | page 5 of 22 absolute maximum ratings table 4 . parameter rating vin to ground ?0.3 v to +7 v vreg to ground ?0.3 v to v in , or +4 v (whichever is less) vout to ground ?0.3 v to v reg , or +4 v (whichever is less) vout_sense to ground ?0.3 v to v reg , or +4 v (whichever is less) vout to vout_sense 0.3 v byp to vout 0.3 v en to ground ?0.3 v to +7 v byp to ground ?0.3 v to v reg , or +4 v (whichever is less) ref to ground ?0.3 v to v reg , or +4 v (whichever is less) ref_sense to ground ?0.3 v to +4 v storage temperature range ?65c to +150c operational junction temperature range ?40c to +125c soldering conditions jedec j - std -020 stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal data absolute maximum ratings apply individually only, not in combination. the adp7156 can be damaged when the junction temperature limits are excee ded. monitoring ambient tempera - ture does not guarantee that t j is within the specified temperature limits. in applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may need to be derated. in applications wi th moderate power dissipation and low printed circuit board (pcb) thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. the junction temperature (t j ) of the devi ce is dependent on the ambient temperature (t a ) , the power dissipation of the device (p d ), and the junction to ambient thermal resistance of the package ( ja ). calculate the maximum junction temperature (t j ) from the ambient temperature (t a ) and power diss ipation (p d ) using the following formula: t j = t a + ( p d ja ) junction to ambient thermal resistance ( ja ) of the package is based on modeling and calculation using a 4 - layer board. the junction to ambient thermal resistance is highly dependent on the app lication and board layout. in applications where high maximum power dissipation exists, close attention to thermal board design is required. the value of ja may vary, depending on pcb material, layout, and environmental conditions. the specified values of ja are based on a 4 - layer, 4 in. 3 in. circuit board. see jesd51 - 7 and jesd51 - 9 for detailed information on the board construction. jb is the junction to board thermal characterization parameter with units of c/w. jb of the package is based on modeling and calculation using a 4 - layer board. jesd51 - 12, guidelines for reporting and using electronic package thermal information , states that thermal characterization parameters are not the same as thermal resistances. jb m easures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance, jb . therefore, jb thermal paths include convection from the top of the package as well as radiation from the package, factors that make jb more useful in real - world applications. maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ) using the following formula : t j = t b + ( p d jb ) see jesd51 - 8 and jesd51 - 12 for more detailed informat ion about jb . thermal resistance ja , jc , and jb are specified for the worst case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 5 . thermal resistance package type ja jc jb unit 10- lead lfcsp 53.8 15.6 29.1 c/w 8 - lead soic 50.4 42.3 30.1 c/w esd caution
adp7156 data she et rev. a | page 6 of 22 pin configurations a nd function descript ions 1 vout notes 1. the exposed p ad is loc a ted on the bot t om of the p ackage. the exposed p ad enhances therma l performace, and it is electrical l y connected t o ground inside the p ackage. connect the exposed p ad t o the ground plane on the board t o ensure proper oper a tion. 2 vout 3 vout_sense 4 by p 5 en 10 vin 9 vin 8 vreg 7 ref 6 ref_sense adp7156 t op view (not to scale) 12937-003 figure 3 . 10 - lead lfcsp pin configuration notes 1. the exposed p ad is loc a ted on the bot t om of the p ackage. the exposed p ad enhances therma l performace, and it is electrical l y connected t o ground inside the p ackage. connect the exposed p ad t o the ground plane on the board t o ensure proper oper a tion. vout vout_sense by p en vin vreg ref ref_sense adp7156 t o p view (not to scale) 1 2 3 4 8 7 6 5 12937-004 figure 4. 8 - lead soic pin configuration table 6 . pin function descriptions pin no. lfcsp soic mnemonic description 1, 2 1 vout regulated output voltage. bypass vout to ground with a 10 f or greater capacitor. 3 2 vout_sense output sense. vout_sense is internally connected to vout with a 10 resistor. connect vout_sense as close to the load as possible. 4 3 byp low noise bypass capacitor. connect a 1 f capacitor from the byp pin to ground to reduce noise. do not connect a load to this pin. 5 4 en enable. drive en high to turn on the regulator; drive en low to turn off the regulator. for automatic startup, connect en to vin. 6 5 ref_sense reference se nse. connect ref_sense to the ref pin. do not connect ref_sense to vout or gnd. 7 6 ref low noise reference voltage output. bypass ref to ground with a 1 f or greater capacitor. short ref_sense to ref for fixed output voltages. do not connect a load to t his pin. 8 7 vreg regulated input supply voltage to low dropout (ldo) amplifier. bypass vreg to ground with a 1 f or greater capacitor. 9, 10 8 vin regulator input supply voltage. bypass vin to ground with a 10 f or greater capacitor. ep exposed pad. the exposed pad is located on the bottom of the package. the exposed pad enhances thermal performance, and it is electrically connected to ground inside the package. connect the exposed pad to the ground plane on the board to ensure proper operation.
data sheet adp7156 rev. a | page 7 of 22 typical performance characteristics v in = v out + 0.5 v or 2.3 v, whichever is greater; v en = v in ; i load = 10 ma; c in = c out = 10 f; c reg = c ref = c byp = 1 f; t a = 25c unless otherwise noted. 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 ? 40 ?20 0 20 40 60 80 100 120 140 i in_sd (a) temper a ture (c) 2.3v 2.5v 3.0v 4.0v 5.0v 5.5v 12937-005 figure 5 . shutdown current (i in_sd ) vs. temperature at various input voltages (v in ), v out = 1.8 v 3.25 3.26 3.27 3.28 3.29 3.30 3.31 3.32 3.33 3.34 3.35 ?40 ?20 0 20 40 60 80 100 120 140 v out (v) temper a ture (c) i l o a d = 0 m a i l o a d = 10 m a i l o a d = 100 m a i l o a d = 600 m a i l o a d = 120 0 m a 12937-006 figure 6 . output voltage (v out ) vs. temperature at various loads, v out = 3.3 v 3.25 3.26 3.27 3.28 3.29 3.30 3.31 3.32 3.33 3.34 3.35 0.1m 1m 10m 100m 1 10 v out (v) i load (a) 12937-007 figure 7 . output voltage (v out ) vs. load current (i load ), v out = 3.3 v 3.25 3.26 3.27 3.28 3.29 3.30 3.31 3.32 3.33 3.34 3.35 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 v out (v) v in (v) i load = 10ma i load = 0ma i load = 100ma i load = 600ma i load = 1200ma 12937-008 figure 8 . output voltage (v out ) vs. input voltage (v in ) at various loads, v out = 3.3 v 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 ?40 ?20 0 20 40 60 80 100 120 140 i gnd (ma) temper a ture (c) i l o a d = 0 m a i l o a d = 10 m a i l o a d = 100 m a i l o a d = 600 m a i l o a d = 120 0 m a 12937-009 figure 9 . ground current (i gnd ) vs. temperature at various loads, v out = 3.3 v 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 0.1m 1m 10m 100m 1 10 i gnd (ma) i load (a) 12937-010 figure 10 . ground current (i gnd ) vs. load current (i load ), v out = 3.3 v
adp7156 data she et rev. a | page 8 of 22 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 i gnd (ma) v in (v) i l o a d = 0 m a i l o a d = 10 m a i l o a d = 100 m a i l o a d = 600 m a i l o a d = 120 0 m a 12937-0 1 1 figure 11 . ground current (i gnd ) vs. input voltage (v in ) at various loads, v out = 3.3 v 0 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 10m 100 1 10 v dropout (v) i load (a) 12937-012 figure 12 . dropout voltage (v dropout ) vs. load current (i load ), v out = 3.3 v 3.00 3.05 3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 v out (v) v in (v) i l o a d = 0 m a i l o a d = 10 m a i l o a d = 100 m a i l o a d = 600 m a i l o a d = 120 0 m a 12937-013 figure 13 . output voltage (v out ) vs. input voltage (v in ) at various loads in dropout, v out = 3.3 v 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 i gnd (ma) v in (v) i l o a d = 0 m a i l o a d = 10 m a i l o a d = 100 m a i l o a d = 600 m a i l o a d = 120 0 m a 12937-014 figure 14 . ground current (i gnd ) vs. input voltage (v in ) at various loads in dropout, v out = 3.3 v 1.75 1.76 1.77 1.78 1.79 1.80 1.81 1.82 1.83 1.84 1.85 ?40 ?20 0 20 40 60 80 100 120 140 v out (v) temper a ture (oc) i l o a d = 0 m a i l o a d = 10 m a i l o a d = 100 m a i l o a d = 600 m a i l o a d = 120 0 m a 12937-015 figure 15 . output voltage (v out ) vs. temperature at various loads, v out = 1.8 v 0.1m 1m 10m 100m 1 10 v out (v) i load (a) 1.75 1.76 1.77 1.78 1.79 1.80 1.81 1.82 1.83 1.84 1.85 12937-016 figure 16 . output voltage (v out ) vs. load current (i load ), v out = 1.8 v
data sheet adp7156 rev. a | page 9 of 22 1.75 1.76 1.77 1.78 1.79 1.80 1.81 1.82 1.83 1.84 1.85 v out (v) i l o a d = 0 m a i l o a d = 10 m a i l o a d = 100 m a i l o a d = 600 m a i l o a d = 120 0 m a 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 v in (v) 12937-017 figure 17 . output voltage (v out ) vs. input voltage (v in ) at various loads, v out = 1.8 v ?40 ?20 0 20 40 60 80 100 120 140 temper a ture (oc) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 i gnd (ma) i l o a d = 0 m a i l o a d = 10 m a i l o a d = 100 m a i l o a d = 600 m a i l o a d = 120 0 m a 12937-018 figure 18 . ground current (i gnd ) vs. temperature at various loads, v out = 1.8 v 0.1m 1m 10m 100m 1 10 i gnd (ma) i load (a) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 12937-019 figure 19 . ground current (i gnd ) vs. load current (i load ), v out = 1.8 v i gnd (ma) 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5 5.3 5.6 v in (v) i l o a d = 0 m a i l o a d = 10 m a i l o a d = 100 m a i l o a d = 600 m a i l o a d = 120 0 m a 12937-020 figure 20 . ground current (i gnd ) vs. input voltage (v in ) at various loads, v out = 1.8 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) i load = 10ma i load = 100ma i load = 600ma i load = 1200ma 12937-021 figure 21 . power supply rejection ratio (psrr) vs. frequency at various loads, v out = 3.3 v, v in = 4.0 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) 900 m v 800 m v 700 m v 600 m v 500 m v 12937-022 figure 22 . power supply rejection ratio (psrr) vs. frequen cy at various headroom voltages, v out = 3.3 v, 1.2 a load
adp7156 data she et rev. a | page 10 of 22 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0.5 0.6 0.7 0.8 0.9 psrr (db) headroom vo lt age (v) 10 hz 100 hz 1 k hz 10 k hz 100 k hz 1 mhz 10 mhz 12937-023 figure 23 . power supply rejection ratio (psrr) vs. headroom voltage at various frequencies, v out = 3.3 v, 1.2 a load ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) i l o a d = 10 m a i l o a d = 100 m a i l o a d = 600 m a i l o a d = 120 0 m a 12937-024 figure 24 . power suppl y rejection ratio (psrr) vs. frequency at various loads, v out = 1.8 v, v in = 2.6 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) 900mv 800mv 700mv 600mv 500mv 12937-025 figure 25 . power supply rejection ratio (psrr) vs. frequency at various headroom voltages, v out = 1.8 v, 1.2 a load ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0.5 0.6 0.7 0.8 0.9 psrr (db) headroom vo lt age (v) 10 hz 100 hz 1 k hz 10khz 100 k hz 1 mhz 10 mhz 12937-026 figure 26 . power supply rejection ratio (psrr) vs. headroom voltage at various frequencies, v out = 1.8 v, 1.2 a load ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) 12937-027 c byp = 1 f c byp = 10 f c byp = 100 f c byp = 1000 f figure 27 . power supply rejection ratio (psrr) vs. frequency at various c byp values , v out = 3.3 v, v in = 4.0 v, 1.2 a load 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 10m 100m 1 10 output noise (v rms) load current (a) 10 h z t o 100 k h z 100 h z t o 100 k h z 12937-028 figure 28 . rms output noise vs. load current
data sheet adp7156 rev. a | page 11 of 22 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1.0 1.5 2.0 2.5 3.0 3.5 output noise (v rms) output vo lt age (v) 10 h z t o 100 k h z 100 h z t o 100 k h z 12937-029 figure 29 . rms output noise vs. output voltage 0.1 1 10 100 1k 10 100 1k 10k 100k 1m 10m noise spectra l densit y (nv/hz) frequenc y (hz) 12937-032 c byp = 1 f c byp = 10 f c byp = 100 f c byp = 1000 f figure 30 . noise spectral density vs. fre quency at various values of c byp 0.1 1 10 100 1k 10k 100k 0.1 1 10 100 1k 10k 100k 1m output noise spectra l densit y (nv/hz) frequenc y (hz) i l o a d = 10 m a i l o a d = 100 m a i l o a d = 600 m a i l o a d = 120 0 m a 12937-033 figure 31 . output noise spectral density vs. frequency at various loads, 0.1 hz to 1 mhz 0.1 1 10 100 1k 10 100 1k 10k 100k 1m 10m noise spectra l densit y (nv/hz) frequenc y (hz) i l o a d = 10 m a i l o a d = 100 m a i l o a d = 600 m a i l o a d = 120 0 m a 12937-034 figure 32 . output noise spectral density vs. frequency at various loads, 10 hz to 10 mhz 1 2 ch1 500ma b w i out v out ch2 5.0mv b w m4.00s a ch1 700ma t 21.10% slew rate = 2.5a/s t 12937-035 figure 33 . load transient response, i load = 100 ma to 1.2 a, v out = 3.3 v, v in = 4.0 v, channel 1 = i out , c hannel 2 = v out 1 2 ch1 500ma b w ch2 5mv b w m4.00s a ch1 690ma t 22.60% i out v out t 12937-036 slew rate = 1.5a/s figure 34 . load transient response, i load = 100 ma to 1.2 a, v out = 3.3 v, v in = 4.0 v, c out = 22 f, channel 1 = i out , c hannel 2 = v out
adp7156 data she et rev. a | page 12 of 22 1 2 ch1 500ma b w ch2 5mv b w m4.00s a ch1 740ma t 21.30% i out v out t slew rate = 2.5a/s 12937-037 figure 35 . load transient response, i load = 100 ma to 1.2 a, v out = 1.8 v, v in = 2.5 v, channel 1 = i out , c hannel 2 = v out 1 2 ch1 500ma b w ch2 5mv b w m4.00s a ch1 740ma t 20.70% i out v out t 12937-038 slew rate = 2.4a/s figure 36 . load transient response, i load = 100 ma to 1.2 a, v out = 1.8 v, v in = 2.5 v, c out = 22 f, channel 1 = i out , c hannel 2 = v out 1 2 ch1 1.0v b w ch2 5mv b w m10.0s a ch1 4.34ma t 21.10% v in v out t slew rate = 1v/s 12937-039 figure 37 . line transient response, 1 v input step, i load = 1.2 a, v out = 3.3 v, v in = 3.8 v, channel 1 = v in , c hannel 2 = v out 1 2 ch1 1.0v b w ch2 2.0mv b w m10.0s a ch1 3.00v t 21.80% v in v out t slew rate = 1v/s 12937-040 figure 38 . line transient response, 1 v input step, i load = 1.2 a, v out = 1.8 v, v in = 2.5 v, channel 1 = v in , c hannel 2 = v out 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 ?2 ?1 0 1 2 3 4 5 6 7 8 v out (v) time (ms) v en 3.3 v 2.5 v 1.8 v 12937-041 figure 39 . v out start - up time after v en rising, at various output voltages, v in = 5 v, c byp = 1 f ?2 0 2 4 6 8 10 12 14 16 18 20 v en 1 f 4.7 f 10 f 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v out (v) time (ms) 12937-042 figure 40 . v out start - up time behavior at various values of c byp , v out = 3.3 v
data sheet adp7156 rev. a | page 13 of 22 theory of operation the adp7156 is an ultralow noise, high psrr linear regulator targeting radio frequency (rf) applications. the input voltage range is 2.3 v to 5.5 v, and it can deliver up to 1.2 a of load current. typical shutdown current consumption is 0.2 a at room temperature. opti mized for use with 10 f ceramic capacitors, the adp7156 provides excellent transient performance. vreg gnd (epad) vout vin en ref ref_sense vout_sense reference shutdown current-limit, thermal protect ota byp internal regulator 12937-043 figure 41 . simplified internal block diagram internally, the adp7156 consists of a reference, an error ampli - fier, and a p - channel mo sfet pass transistor. the output current is delivered via the pmos pass device, which is controlled by the error amplifier. the error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. if the fe edback voltage is lower than the refer ence voltage, the gate of the pmos device is pulled lower, allowing more current to pass and increasing the output voltage. if the feedback voltage is higher than the reference voltage, the gate of the pmos device is p ulled higher, allowing less current to pass and decreasing the output voltage. by heavily filtering the reference voltage, the adp7156 can achieve 1.7 nv/hz typical output noise spectral density from 10 khz to 1 mhz. because the error amplifier is always in unit y gain, the output noise is independent of the output voltage. the adp7156 uses the en pin to enable and disable the vout pin under normal operating conditions. when en is high, vout turns on, and when en is low, vout turns off. for automatic startup, tie en to vi n. 4v 7v 4v 4v 4v 4v 4v 4v 4v 4v 7v 7v 4v vin vreg ref ref_sense by p vout vout_sense en gnd (e p ad) 12937-044 figure 42 . simplified esd protection block diagram the esd protection devices are shown in the block diagram as zener diodes (see figure 42).
adp7156 data sheet rev. a | page 14 of 22 applications informa tion adi sim power design tool the adp7156 is supported by the adisimpower ? design tool set. adisimpower is a collection of tools that produce complete power designs optimized for a specific design goal. the se tools enable the user to generate a full schematic, bill of materials, and calculat e performance within minutes. adisimpower can optimize designs for cost, area, efficiency, and device count, taking into consideration the operating conditions and limita - tions of the ic and all real external components. for more information about, and to obtain the adisimpower design tools, visit www.analog.com/ adisimpower . capacitor selection multilayer ceramic capacitors (mlccs) combine small size, low esr, low esl, and a wide operating temperature range, making them an ideal choice for bypass capacitors. they are not without faults, however. depending on the d ielectric material, the capacitance can vary dramatically with temperature, dc bias, and ac signal level. therefore, selecting the proper capacitor results in the best circuit performance. output capacitor the adp7156 is designed for operation with ceramic capacitors but functions with most commonly used capacitors when care is taken with regard to the esr value. the esr of the output capaci - tor affects the stability of the ldo control loop. a minimum of 10 f capacitance with an esr of 0.1 ? or less is recommended to ensure the stability of the adp7156 . output capacitance also affects transient response to changes in load current. using a larger value of output capacitance improves the transient response of the adp7156 to large changes in load current. figure 43 shows the transient responses for an output capacitance value of 10 f. 1 2 ch1 1.0v b w ch2 2.0mv b w m4.0s a ch1 700mv t 21.10% v out i out t slew rate = 2.5a/s 12937-045 figure 43 . output transient response, v out = 3.3 v, c out = 10 f, channel 1 = load current, channel 2 = v out input and vreg capacitor connecting a 10 f capacitor from vin to ground reduces the circuit sensitivity to pcb layout, especially when long input traces or high source impedance are encountered. to maintain the best possible stability and psrr performance, connect a 1 f or greater capacitor from vreg to ground . ref capacit or the ref capacitor, c ref , is necessary to stabilize the reference amplifier. connect at 1 f or greater capacitor between ref and ground . byp capacitor the byp capacitor , c byp , is necessary to filter the reference buffer. a 1 f capacitor is typically connected between byp and ground . capacitors as small as 0.1 f can be used; however, the output noise voltage of the ldo increases as a result. in addition, the byp capacitor valu e can be increased to reduce the noise below 1 khz at the expense of increasing the start - up time of the ldo regulator. very large values of c byp signifi - cantly reduce the noise below 10 hz. tantalum capacitors are recommended for capacitors larger than ap proximately 33 f because solid tantalum capacitors are less prone to microphonic noise issues. a 1 f ceramic capacitor in parallel with the larger tantalum capacitor is recommended to ensure good noise performance at higher frequencies. 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1 10 100 1000 output noise (v rms) c byp (f) 10 h z t o 100 k h z 100 h z t o 100 k h z 12937-046 figure 44 . rms output noise vs. bypass capacitance (c byp )
data sheet adp7156 rev. a | page 15 of 22 0.1 1 10 100 1k 10 100 1k 10k 100k 1m 10m noise spectra l densit y (nv/hz) frequenc y (hz) c byp = 1 f c byp = 10 f c byp = 100 f c byp = 1000 f 12937-047 figure 45 . noise spectral density vs. frequency at various c byp values capacitor properties any good quality ceramic capacitors can be used with the adp7156 if they meet the minimum capacitance and maxi mum esr requirements. ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over tempera - ture and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary tempera - ture range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6 .3 v to 50 v are recommended. however, y5v and z5u dielectrics are not recommended because of their poor temperature and dc bias characteristics. figure 46 depicts the capacitance vs. dc bias voltage of a 1206, 10 f, 10 v, x5r capacitor. the voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. in general, a capacitor in a larger package or higher voltage ra ting exhibits better stability. the temperature variation of the x5r dielectric is ~15% over the ?40c to +85c temperature range and is not a function of package or voltage rating. capacitance (f) dc bias voltage (v) 10 0 4 8 2 6 0 12 10 8 6 4 2 12937-048 figure 46 . capacitance vs. dc bias voltage use equation 1 to determine t he worst case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage. c eff = c bias (1 ? tempco ) (1 ? tol ) (1) where: c eff is the wors t case capacitance. c bias is the effective capa citance at the operating voltage. tempco is the worst case capacitor temperature coefficient. tol is the worst case component tolerance. in this example, the worst case temperature coefficient (tempco) over ?40c to +85c is assumed to be 15% for an x5r dielectric. the tolerance of the capacitor (tol) is assumed to be 10%, and c bias is 9.72 f at 5 v, as shown in figure 46. substituting these values in equation 1 yields c eff = 9.72 f (1 ? 0.15) (1 ? 0.1) = 7.44 f therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ldo over temperature and tolerance at the chosen output voltage. to guarantee the performance of the adp7156 , it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacit ors be evaluated for each application. undervoltage locout (uvlo) the adp7156 also incorporates an internal uvlo circuit to disable the output voltage when the input voltage is less than the minimum input voltage rating of the regulator. the upper and lower thresholds are internally fixed with 200 mv (typical) of hysteresis . 0 0.5 1.0 1.5 2.0 2.5 1.9 2.0 2.1 2.2 2.3 v out (v) v in (v) +12 5 c +2 5 c ?4 0 c 12937-049 figure 47 . typical uvlo behavior at various temperatures, v out = 3.3 v figure 47 shows the typical behavior of the uvlo function. this hysteresis prevents on/off oscillations that can occur when caused by noise on the input voltage as it passes through the threshold point s.
adp7156 data sheet rev. a | page 16 of 22 programmable precisi on enable the adp7156 uses the en pin to enab le and disable the vout pin under normal operating conditions. as shown in figure 48 , when a rising voltage on en crosses the upper threshold, nominal ly 1.22 v, v out turns on. when a falling voltage on en crosses the lower threshold, nominally 1.13 v, v out turns off. the hysteresis of the en threshold is typically 90 mv. adp7156 includes a discharge resistor on each vout, vreg, ref , and byp pin. the se resistors turn on when the device is disabled, and helps to d i scharge the associated capacitor very quickly. 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 1.00 1.05 1.10 1.15 1.20 1.25 1.30 v out (v) en pin vo lt age (v) ? 40 c ? 5 c 25 c 85 c 125 c 12937-050 figure 48 . typical v out response to en pin operation 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 ?2 ?1 0 1 2 3 4 5 6 7 8 v out (v) time (ms) v en v out 12937-051 figure 49 . typical v out response to en pin operation (v en ), v out = 3.3 v, v in = 5 v, c byp = 1 f 1.100 1.125 1.150 1.175 1.200 1.225 1.250 2.5 3.0 3.5 4.0 4.5 5.0 5.5 en precision threshold (v) input vo lt age (v) en rising en f alling 12937-052 figure 50 . typical en precision threshold vs. input voltage (v in ) the uppe r and lower thresholds are user - programmable and can be set higher than the nominal 1.22 v threshold by using two resistors. determine the resistance values, r en1 and r en2 , from r en1 = r en2 ( v en ? 1.22 v)/1.22 v where: r en2 typically ranges from 10 k to 100 k. v en is the desired turn - on voltage. the hysteresis voltage increases by the factor ( r en1 + r en2 )/ r en 2 for the example shown in figure 51 , the en threshold is 2.44 v with a hysteresis of 200 mv. vout vout_sense ref_sense ref vin en adp7156 gnd (epad) c ref 1f c in 10f c out 10f off on v in = 3.8v v out = 3.3v byp c byp 1f r en1 100k r en2 100k vreg c reg 1f 12937-053 figure 51 . typical en pin voltage divider figure 51 shows the typical voltage divider configuration of the en pin. this conf iguration prevents on/off oscillations that can occur due to noise on the en pin as it passes through the threshold points.
data sheet adp7156 rev. a | page 17 of 22 start-up time the adp7156 uses an internal soft start to limit the inrush current when the output is enabled. the start-up time for a 3.3 v output is approximately 1.2 ms from the time the en active threshold is crossed to when the output reaches 90% of its final value. the rise time in seconds of the output voltage (10% to 90%) is approximately 0.0012 c byp where c byp is measured in microfarads. ?202468101214161820 v en 1f 4.7f 10f 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v out (v) time (ms) 12937-054 figure 52. typical start-up behavior with c byp = 1 f to 10 f ?20 0 20 40 60 80 100 120 140 160 v en 10f 47f 100f 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v out (v) time (ms) 12937-055 figure 53. typical start-up behavior with c byp = 10 f to 100 f ref, byp, and vreg pins ref, byp, and vreg generate voltages internally (v ref , v byp , and v reg ) that require external bypass capacitors for proper operation. do not, under any circumstances, connect any loads to these pins, because doing so compromises the noise and psrr performance of the adp7156 . using larger values of c byp , c ref , and c reg is acceptable but can increase the start-up time, as described in the start-up time section. current-limit and thermal shutdown the adp7156 is protected against damage due to excessive power dissipation by current and thermal overload protection circuits. the adp7156 is designed to current limit when the output load reaches 1.8 a (typical). when the output load exceeds 1.8 a, the output voltage is reduced to maintain a constant current limit. when the adp7156 junction temperature exceeds 150c, the thermal shutdown circuit turns off the output voltage, reducing the output current to zero. extreme junction temperature can be the result of high current operation, poor circuit board design or high ambient temperature. a 15c hysteresis is included so that the adp7156 does not return to operation after thermal shutdown until the on-chip temperature falls below 135c. when the device exits thermal shutdown, a soft start is initiated to reduce the inrush current. current-limit and thermal shutdown protections are intended to protect the device against accidental overload conditions. for example, a hard short from vout to ground or an extremely long soft start timer usually causes thermal oscillations between the current limit and thermal shutdown. thermal considerations in applications with a low input to output voltage differential, the adp7156 does not dissipate much heat. however, in applica- tions with high ambient temperature and/or high input voltage, the heat dissipated in the package may become large enough that it causes the junction temperature of the die to exceed the maximum junction temperature of 125c. the junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown in equation 2. to guarantee reliable operation, the junction temperature of the adp7156 must not exceed 125c. to ensure that the junction temperature stays below this maximum value, the user must be aware of the parameters that contribute to junction temperature changes. these parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air ( ja ). the ja number is dependent on the package assembly compounds that are used and the amount of copper used to solder the exposed pad (ground) to the pcb.
adp7156 data sheet rev. a | page 18 of 22 table 7 shows the typical ja values of the 8 - lead soic and 10- lead lfcsp packages for various pcb copper sizes. table 8 shows the typical jb values of the 8 - lead soic and 10 - lead lfcsp. table 7 . typical ja values ja (c/w) copper size (mm 2 ) 10- lead lfcsp 8 - lead soic 25 1 130.2 123.8 100 93.0 90.4 500 65.8 66.0 1000 55.6 56.6 6400 44.1 45.5 1 device soldered to minimum size pin traces. table 8 . typical jb values package jb (c/w) 10- lead lfcsp 29.1 8 - lead soic 30.1 calculate t he junction temperature (t j ) of the adp7156 from the following equation: t j = t a + ( p d ja ) (2) where: t a is the ambient temperature. p d is the power dissipation in the die, given by p d = (( v in ? v out ) i load ) + ( v in i gnd ) (3) where: v in and v out are the input and output voltages, respectively. i load is the load current. i gnd is the ground current. power dissipation caused by ground current is quite small and can be ignored. therefore, the junction temperature equation simplifie s to the following: t j = t a + ((( v in ? v out ) i load ) ja ) (4) as shown in equation 4, for a given ambient temperature, input to output voltage differential, and continuous load current, a minimum copper size requirement exists for the pcb to ensure that the junction temperatu re does not rise above 125 c. the heat dissipation from the package can be improved by increas - ing the amount of copper attached to the pins and exposed pad of the adp7156 . adding thermal planes underneath the package also improves thermal performance. however, as shown in table 7 , a point of diminishing returns is eventually reached, beyond which an increase in the copper area does not yield significant reduc - tion in t he junction to ambient thermal resistance. figure 54 to figure 59 show junction temperature calculations for various ambient temperatures, power dissipation, and areas of pcb copper. 0 20 40 60 80 100 120 140 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 junction temperature (c) total power dissipation (w) 6400mm 2 500mm 2 25mm 2 t j max 12937-056 figure 54 . junction temperature vs. total power dissipation for the 10 - lead lfcsp, t a = 25c 20 40 60 80 100 120 140 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 junction temperature (c) total power dissipation (w) 6400mm 2 500mm 2 25mm 2 t j max 12937-057 figure 55 . junction temperature vs. total power dissipation for the 10 - lead lfcsp, t a = 50c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.9 0.8 1.0 junction temperature (c) total power dissipation (w) 6400mm 2 500mm 2 25mm 2 t j max 80 85 90 95 100 105 1 10 1 15 120 125 130 12937-058 figure 56 . junction temperature vs. total power dissipation for the 10 - lead lfcsp, t a = 85c
data sheet adp7156 rev. a | page 19 of 22 0 20 40 60 80 100 120 140 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 junction temperature (c) total power dissipation (w) 6400mm 2 500mm 2 25mm 2 t j max 12937-059 figure 57 . junction temperature vs. total power dissipation for the 8 - lead soic, t a = 25c 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 junction temperature (c) total power dissipation (w) 40 50 60 70 80 90 100 1 10 120 130 6400mm 2 500mm 2 25mm 2 t j max 12937-060 figure 58 . junction temperature vs. total power dissipation for the 8 - lead soic, t a = 50c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.9 0.8 1.0 total power dissipation (w) 80 85 90 95 100 105 1 10 1 15 120 125 130 junction temperature (c) 6400mm 2 500mm 2 25mm 2 t j max 12937-061 figure 59 . junction temperature vs. total power dissipation for the 8 - lead soic, t a = 85c thermal characterization parameter ( jb ) when the evaluatio n board te mperature is known, use the thermal characteriza tion parameter, jb , to estimate the jun ction temperature rise (see figure 60 and figure 61 ). calculate the m aximum junction temperature (t j ) from the evaluation board tempera ture (t b ) and power dissipation (p d ) using the following formula: t j = t b + ( p d jb ) (5) the typical valu e of jb is 29.1c/w for the 10 - lead lfcsp package and 30.1c/w for the 8 - lead soic package. 0 20 40 60 80 100 120 140 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 junction temper a ture (c) t ot al power dissi pa tion (w) t b = 2 5 c t b = 5 0 c t b = 6 5 c t b = 8 5 c t j m a x 12937-062 figure 60 . junction temperature vs. total power dissipation for the 10 - lead lfcsp 0 20 40 60 80 100 120 140 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 junction temper a ture (c) t ot al power dissi pa tion (w) t b = 2 5 c t b = 5 0 c t b = 6 5 c t b = 8 5 c t j m a x 12937-063 figure 61 . junction temperature vs. total power dissipation for the 8 - lead soic
adp7156 data sheet rev. a | page 20 of 22 printed circuit boar d (pcb) layout consi derations place the input capacitor as close as possible between the v in pin and ground . place the output capacitor as close as possible between the vout pin and ground . place the bypass capacitors (c reg , c ref , and c byp ) for v reg , v ref , and v byp close to the respec - tive pins (vreg, ref, and byp) and ground . the use of a 0805, 0603, or 0402 siz e capacitor achieves the smallest possible footprint solution on boards where area is limited. maximize the amount of ground metal for the exposed pad, and use as many vias as possible on the component side to improve thermal dissipation. 12937-064 figure 62 . sample 10 - lead lfcsp pcb layout 12937-065 figure 63 . sample 8 - lead soic pcb layout
data sheet adp7156 rev. a | page 21 of 22 outline dimensions 2.48 2.38 2.23 0.50 0.40 0.30 10 1 6 5 0.30 0.25 0.20 pin 1 index are a se a ting plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pa d 3.10 3.00 sq 2.90 pin 1 indic a t or (r 0.15) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 02-05-2013-c t o p view bottom view 0.20 min figure 64 . 10 - lead lead frame chip scale package [lfcsp] 3 mm 3 mm body and 0.75 mm package height (cp - 10 - 9) dimensions shown in millimeters compliant t o jedec s t andards ms-012-a a 06-02-20 1 1-b 1.27 0.40 1.75 1.35 2.29 2.29 0.356 0.457 4.00 3.90 3.80 6.20 6.00 5.80 5.00 4.90 4.80 0.10 max 0.05 nom 3.81 ref 0.25 0.17 8 0 0.50 0.25 45 coplanarit y 0.10 1.04 ref 8 1 4 5 1.27 bsc se a ting plane for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. bot t om view top view 0.51 0.31 1.65 1.25 figure 65 . 8 - lead standard small outline package, with exposed pad [soic_n_ep] narrow body (rd - 8- 1) dimensions shown in millimeters
adp7156 data sheet rev. a | page 22 of 22 ordering guide model 1 , 2 temperature range output voltage (v) package description package option branding adp7156 acpz - 1.2-r7 ?40c to +125c 1.2 10- lead lfcsp cp -10 -9 lst adp7156 acpz -1. 8- r7 ?40c to +125c 1.8 10- lead lfcsp cp -10 -9 lsu adp7156acpz - 2.0-r7 ?40c to +125c 2.0 10- lead lfcsp cp -10 -9 ltq adp7156 acpz - 2.5-r7 ?40c to +125c 2.5 10- lead lfcsp cp -10 -9 lsv adp7156 acpz - 2.8-r7 ?40c to +125c 2.8 10- lead lfcsp cp -10 -9 lsw adp7156 acpz - 3.0-r7 ?40c to +125c 3.0 10- lead lfcsp cp -10 -9 lsy adp7156 acpz - 3.3-r7 ?40c to +125c 3.3 10- lead lfcsp cp -10 -9 lsz adp7156ardz - 1.2 -r7 ?40c to +125c 1.2 8- lead soic_n_ep rd -8-1 adp7156ardz - 1.8 -r7 ?40c to +125c 1.8 8- lead soic_n_ep rd -8-1 adp7156ardz - 2.0 -r7 ?40c to +125c 2.0 8- lead soic_n_ep rd -8-1 adp7156ardz - 2.5 -r7 ?40c to +125c 2.5 8- lead soic_n_ep rd -8-1 adp7156ardz - 2.8 -r7 ?40c to +125c 2.8 8- lead soic_n_ep rd -8-1 adp7156 ardz - 3.0 - r7 ?40c to +125c 3.0 8 - lead soic_n_ep rd - 8 - 1 adp7156ardz - 3.3 -r7 ?40c to +125c 3.3 8- lead soic_n_ep rd -8-1 adp7156 cp - 3.3evalz evaluation board 1 z = rohs compliant part. 2 to order a device with voltage op tions of 1.3 v, 1.5 v, 1.6 v, 2.2 v, 2.6 v, 2.7 v, 2.9 v, 3.1 v, and 3.2 v, co ntact your local analog devices, inc., sales or distribution representative. ? 2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d12937 -0-5 /16( a)

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